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FemtoClockTM Crystal-to-LVDS/LVCMOS Frequency
General Description
ICS8402015I is a low phase noise Clock Synthesizer and is a member of the HiPerClockSTM family of high HiPerClockSTM performance clock solutions from IDT. The device provides three banks of outputs and a reference clock. Each bank can be enabled by using output enable pins. A 25MHz or 50MHz, 18pF parallel resonant crystal is used to generate 25MHz LVCMOS, 125MHz LVCMOS and 125MHz LVDS outputs. ICS8402015I is packaged in a small, 32-pin VFQFN package that is optimum for applications with space limitations.
ICS8402015I
DATASHEET
Features
*
Three banks of outputs: Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz or 50MHz Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz Bank C: three differential LVDS outputs at 125MHz Reference LVCMOS/LVTTL output at 25MHz
ICS
* * * * * * *
Crystal input frequency: 25MHz Maximum output frequency: 125MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (637kHz - 62.5MHz): 0.373ps (typical) LVDS output RMS phase jitter @ 25MHz, using a 25MHz crystal (12kHz - 1MHz): 0.64ps (typical) LVCMOS output Full 3.3V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package
Pin Assignment
XTAL_OUT XTAL_IN GND OE1 OE0 OE2 GND VDDA
32 31 30 29 28 27 26 25 VDDO_REF REF_OUT GND GND QA0 QA1 QA2 VDDO_A 1 2 3 4 5 6 7 8 9
VDDO_B
24 23 22 21 20 19 18 17 10 11 12 13 14 15 16
GND GND MR QB0 QB1 QB2 VDD
VDDO_C nQC2 QC2 nC1 QC1 nQC0 QC0 VDDO_C
ICS8402015I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
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FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Block Diagram
OE1 = Pullup
OE[2:0] OE0, OE2 = Pulldown
3
OE LOGIC
LVCMOS - 25MHz or 50MHz
QA0 QA1 QA2
/10 /20
25MHz
XTAL_IN
LVCMOS - 125MHz
OSC
XTAL_OUT
Phase Detector
VCO
500MHz
QB0 QB1 QB2
/4
/20
LVDS - 125MHz
QC0 nQC0
/4
QC1 nQC1 QC2 nQC2
MR Pulldown
LVCMOS - 25MHz
REF_OUT
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Table 1. Pin Descriptions
Number 1 2 3, 4, 13, 16, 25, 32 5, 6, 7 8 9 10, 11, 12 14 15 17, 24 18, 19 20, 21 22, 23 26 27, 29 28 30, 31 Name VDDO_REF REF_OUT GND QA0, QA1, QA2 VDDO_A VDDO_B QB0, QB1, QB2 MR VDD VDDO_C QC0, nQC0 QC1, nQC1 QC2, nQC2 VDDA OE0, OE2 OE1 XTAL_IN, XTAL_OUT Power Output Power Output Power Power Output Input Power Power Output Output Output Power Input Input Input Pulldown Pullup Pulldown Type Description Output supply pin for REF_OUT output. Reference clock output. LVCMOS/LVTTL interface levels. Power supply ground. Single-ended Bank A clock outputs.LVCMOS/LVTTL interface levels. Power output supply pin for Bank A LVCMOS outputs. Power output supply pin for Bank B LVCMOS outputs. Single-ended Bank B clock outputs.LVCMOS/LVTTL interface levels. Master reset, resets the internal dividers. During reset, LVCMOS outputs are pulled LOW, and LVDS outputs are pulled LOW and HIGH (QCx pulled LOW, nQCx pulled HIGH). LVCMOS/LVTTL interface levels. Core supply pin. Power output supply pin for Bank C LVDS outputs. Differential Bank C clock outputs. LVDS interface levels. Differential Bank C clock outputs. LVDS interface levels. Differential Bank C clock outputs. LVDS interface levels. Analog supply pin. Output enable and configuration pins. See Table 3. LVCMOS/LVTTL interface levels. Output enable and configuration pin. See Table 3. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance QA[0:2], QB[0:2], REF_OUT VDD, VDDO_A, VDDO_B, VDDO_C = 3.465V Test Conditions Minimum Typical 4 15 51 51 20 Maximum Units pF pF k k
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FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Function Table
Table 3. OE Function and ConfigurationTable
Inputs Bank A OE2 0 0 0* 0 1 1 1 1 *Default OE1 0 0 1* 1 0 0 1 1 OE0 0 1 0* 1 0 1 0 1 A0 25 25 25 25 50 25 50 Hi-Z A1 Hi-Z Hi-Z 25 25 Hi-Z 25 50 Hi-Z A2 Hi-Z Hi-Z Hi-Z 25 Hi-Z Hi-Z Hi-Z Hi-Z B0 Hi-Z 125 Hi-Z 125 Hi-Z 125 Hi-Z Hi-Z Output Frequency (MHz) Bank B B1 Hi-Z Hi-Z Hi-Z 125 Hi-Z 125 Hi-Z Hi-Z B2 Hi-Z Hi-Z Hi-Z 125 Hi-Z Hi-Z Hi-Z Hi-Z C0 125 125 125 125 125 125 125 Hi-Z Bank C C1 Hi-Z Hi-Z 125 125 Hi-Z 125 125 Hi-Z C2 Hi-Z Hi-Z Hi-Z 125 Hi-Z Hi-Z Hi-Z Hi-Z
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO (LVCMOS) Outputs, IO (LVDS) Continuos Current Surge Current Operating Temperature Range, TA Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO_LVCMOS + 0.5V 10mA 15mA -40C to +85C 37C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V5%, TA = -40C to 85C
Symbol VDD VDDA Parameter Core Supply Voltage Analog Supply Voltage Test Conditions Minimum 3.135 VDD - 0.36 Typical 3.3 3.3 Maximum 3.465 VDD Units V V
VDDO_A, VDDO_B, Output Supply Voltage VDDO_C, VDDO_REF IDD IDDA IDDO_A, IDDO_B, IDDO_C, IDDO_REF Power Supply Current Analog Supply Current
3.135
3.3
3.465
V
30 36
mA mA
Total Output Supply Current
Outputs Unused
26
mA
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FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_REF = 3.3V5%, TA = -40C to 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage OE1 OE0, OE2, MR OE1 OE0, OE2, MR QA0:QA2, QB0:QB2, REF_OUT QA0:QA2, QB0:QB2, REF_OUT VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V VDD = 3.465V VDDO_REF = 3.3V5%, IOH = -12mA -150 -5 2.6 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A V
IIL
VOH
VOL
VDDO_REF = 3.3V5%, IOL = 12mA
0.5
V
Table 4D. LVDS DC Characteristics, VDD = VDDO_C = 3.3V5%, TA = -40C to 85C
Symbol VOD VOD VOS VOS IOz IOFF IOSD IOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Power Off Leakage Differential Output Short Circuit Current Output Short Circuit Current -10 -20 -3.5 -3.5 1.325 1.4 Test Conditions Minimum 300 Typical 450 Maximum 575 50 1.575 50 +10 +20 -5 -5 Units mV mV V mV A A mA mA
Table 5. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance Shunt Capacitance Test Conditions Minimum Typical Fundamental 25 50 7 MHz Maximum Units
pF
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Table 6. AC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V5%, TA = -40C to 85C
Symbol Parameter QA[0:2] QA[0:1] fout Output Frequency QB[0:2] QC[0:2]/ nQC[0:2] REF_OUT QA0:QA2, REF_OUT tjit(O) RMS Phase Noise Jitter; NOTE 1 QB0:QB2 QC0:QC2 tsk(b) Bank Skew; NOTE 2, 3 Output Rise/Fall Time QA[0:2], QB[0:2] QC[0:2]/nQC[0:2] QA[0:2], QB[0:2], REF_OUT QC[0:2]/ nQC[0:2] QA[0:2], QB[0:2], REF_OUT QC[0:2]/ nQC[0:2] 20% to 80% 20% to 80% 0.425 145 48 48 25MHz, Integration Range: 12kHz - 1MHz 125MHz, Integration Range: 637kHz - 62.5MHz 125MHz, Integration Range: 637kHz - 62.5MHz Test Conditions Minimum Typical 25 50 125 125 25 0.642 0.389 0.373 45 35 1.15 415 52 52 Maximum Units MHz MHz MHz MHz MHz ps ps ps ps ps ns ps % %
tR / t F
odc
Output Duty Cycle
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
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Parameter Measurement Information
1.65V5% 1.65V5%
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD, VDDO_C VDDA LVDS
Qx
VDD, VDDO_A, VDDO_B
SCOPE
VDDA
nQx GND
LVCMOS
Qx
-1.65V5%
3.3V LVDS Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
Phase Noise Plot
nQC[0:2]
Noise Power
Qx[0:2]
Phase Noise Mask
nQC[0:2] Qx[0:2]
f1
Offset Frequency
tsk(b)
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Where X = Bank A, Bank B or Bank C outputs
RMS Phase Jitter
Bank Skew
V
QA[0:2], QB[0:2]
DDO_CMOS
nQC{0:2] QC{0:2]
2
t PW
t
PERIOD
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
odc =
t PW t PERIOD
x 100%
Single-Ended Output Duty Cycle/Pulse Width/Period
Differential Output Duty Cycle/Pulse Width/Period
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Parameter Measurement Information, continued
nQC{0:2]
80% 20% tR
80% 20% tF
80%
80% VOD
QA[0:2], QB[0:2]
QC{0:2]
20% tR tF
20%
LVCMOS Output Rise/Fall Time
LVDS Output Rise/Fall Time
out
IOZ DC Input
VDD out
3.3V5% POWER SUPPLY
+
Float GND
_
LVDS
IOZ
out
DC Input
LVDS
out
IOSD
High Impedance Leakage Current Setup
Differential Output Short Circuit Setup
VDD VDD out
DC Input
LVDS
100
VOD/ VOD out
out
Differential Output Voltage Setup
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out
DC Input
LVDS
VOS/ VOS
Offset Voltage Setup
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Parameter Measurement Information, continued
VDD out
IOS
DC Input
LVDS
IOSB out
LVDS
IOFF
VDD
Output Short Circuit Current Setup
Power Off Leakage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8402015I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDO_A, VDDO_B, VDDO_C, and VDDO_REF should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS outputs should be terminated with 100 resistor between the differential pair.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no trace attached.
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FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS8402015I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
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FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
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VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Schematic Example
Figure 6 shows an example of ICS8402015I application schematic. In this example, the device is operated at VDD = VDDO_REF = VDDO_A = VDDO_B = VDDO_C = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for
Logic Input Pin Examples
QC2 VDD
frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two example of LVDS for receiver without built-in termination and one example of LVCMOS are shown in this schematic.
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install nQC2 QC2 Zo = 50 Ohm + Zo = 50 Ohm R1 100 -
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
VDDO
nQC2
QC0 VDD 24 23 22 21 20 19 18 17 U1 R2 10 C3 0.01uF
VDD=3.3V VDDO=3.3V
VD D O _C nQ C 2 QC 2 nQ C 1 QC 1 nQ C 0 QC 0 VD D O _C
VDDA C6 10uF OE0 OE1 OE2 25 26 27 28 29 30 31 32
VDD 16 15 14 13 12 11 10 9
nQC0
XTAL_IN C1 27pF 18pF X1 25MHz XTAL_OUT C2 27pF
VD D O _R EF R EF _O U T GN D GN D Q A0 Q A1 Q A2 VD D O _A
GND VDDA OE0 OE1 OE2 XTAL_IN XTAL_OUT GND
GND VDD MR GND QB2 QB1 QB0 VDDO_B
VDD MR QB2 QB2 C4 0.1uF
QC0
Zo = 50 Ohm
R3 50
+
nQC0 1 2 3 4 5 6 7 8
Zo = 50 Ohm
C5 0.1uF R4 50
-
Alternate LVDS Termination
VDDO (U1:1) VDDO (U1:8) (U1:9) C7 0.1uF C8 0.1uF C9 0.1uF (U1:17) C10 0.1uF (U1:24) C11 0.1uF
R5 30
Zo = 50 Ohm
LVCMOS
REF_OUT
R6 30
Zo = 50 Ohm
LVCMOS
Figure 6.ICS8402015I Schematic Example
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FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8402015I. Equations and example calculations are also provided. 1. Power Dissipation.
The total power dissipation for the ICS8402015I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation * Power (core, LVDS) = VDD_MAX * (IDD + IDDO_X + IDDA) = 3.465V * (30mA + 26mA + 36mA) = 318.78mW
LVCMOS Output Power Dissipation * * * Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.7mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.7mA)2 = 12.25mW per output Total Power Dissipation on the ROUT
Total Power (ROUT) = 12.25mW * 6 = 73.5mW
Total Power Dissipation * Total Power = Power (core, LVDS) + Total Power (ROUT) = 318.78mW + 73.5mW = 392.28mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.392W * 37C/W = 99.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 37.0C/W 1 32.4C/W 2.5 29.0C/W
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Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 37.0C/W 1 32.4C/W 2.5 29.0C/W
Transistor Count
The transistor count for ICS8402015I is: 2311
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
are Even
OR
To p View
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9.
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Ordering Information
Table 10. Ordering Information
Part/Order Number 8402015AKILF 8402015AKILFT Marking ICS02015AIL ICS02015AIL Package "Lead-Free" 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev A Table T10 Page 17 Description of Change Ordering Information Table - added "I" in part/order number. Date 6/25/09
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(c)2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
6024 Silver Creek Valley Road San Jose, California 95138
Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support netcom@idt.com +480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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